FPGA architecture with deep look-up table RAMs

ABSTRACT

A configurable logic block (CLB) having a plurality of identical configurable logic element CLE) slices is provided. Each CLE slice includes a plurality of function generators (lookup tables) that can be configured to form a random access memory (RAM). The width and depth of the RAM are selectable by controlling the routing of signals within the CLE slices. A hierarchy of wide function multiplexers (F 5 , F 6 , and F 7  multiplexers) are provided to selectively route read data values from the lookup tables. Another set of multiplexers is used to selectively route write data values to the lookup tables. These multiplexers can be configured to provide a single write data value to all of the lookup tables to form a deep RAM. Alternatively, these multiplexers can be configured to provide one write data value to half of the lookup tables, and another write data value to the other half of the lookup tables. This pattern repeats down to the level where these multiplexers can be configured to provide a different write data value to each of the lookup tables. A write control circuit is also provided in each CLE slice to provide write enable signals to the lookup tables in a manner consistent with the selected RAM size.

RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent application Ser. No. 09/253,313 filed Feb. 18, 1999, which is a continuation in part of U.S. patent application Ser. No. 08/754,421, filed Nov. 22, 1996, now U.S. Pat. No. 5,889,413, the content of which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to an architecture for enabling random access memory (RAM) structures in configurable logic blocks (CLBS) of a field programmable gate array (FPGA).

BACKGROUND OF THE INVENTION

Xilinx, Inc. the assignee of the present application, manufactures FPGAs, the complexity of which continues to increase. Freeman in U.S. Pat. Reissue No. 34,363, incorporated herein by reference, which is a re-issue of original U.S. Pat. No. 4,870,302, describes the first FPGA. An FPGA is an integrated circuit chip which includes a plurality of programmable input/output pads, a plurality of configurable logic elements, and a programmable interconnect structure for interconnecting the plurality of logic elements and pads. Each logic element implements a logic function of the n inputs to the logic element according to how the logic element has been configured. Logic functions may use all n inputs to the logic element or may use only a subset thereof. A few of the possible logic functions that a logic element can be configured to implement are: AND, OR, XOR, NAND, NOR, XNOR and mixed combinations of these functions.

One disclosed implementation of the logic element includes a configurable lookup table which is internal to the logic element and which includes 2^(n) individual memory cells, where n is the number of input signals the lookup table can handle. At configuration, in this architecture a bitstream programs the individual memory cells of the lookup table with a desired function by writing the truth table of the desired function to the individual memory cells. Although the programming is described as being performed serially, other techniques for parallel programming are also known.

One memory cell architecture appropriate for use in the lookup tables is shown in FIG. 1 and described by Hsieh in U.S. Pat. No. 4,821,233, incorporated herein by reference. A memory cell of this architecture is programmed by applying the value to be written to the memory cell on the data input line, “Data,” and strobing the corresponding address line, “ADDR.” Further, although this architecture uses five transistors, other known configurations, e.g., six transistor static memory cells, also are appropriate choices for implementing the memory cells of the lookup table. As shown in FIG. 1, inverter 726 may be included to increase the drive of memory cell 700, and avoid effecting the value stored in memory cell 700 unintentionally via charge sharing with the read decoder.

After configuration, to use a lookup table, the input lines of the configured logic element act as address lines which select a corresponding memory cell in the lookup table. For example, a logic element configured to implement a two-input NAND gate would output the corresponding value {1,1,1,0} contained in the one of the four memory cells corresponding to the current input pair {00, 01, 10, 11}, respectively.

This selection is performed by a decoding multiplexer which selects a memory cell from the lookup table on the basis of the logic levels of the input lines. A block diagram of an exemplary four-input lookup table composed of 16 memory cells 700 ₁ through 700 ₁₆ and a decoding multiplexer 200 is shown in FIG. 2. The multiplexer propagates a value stored in one of the memory cells 700 ₁-700 ₁₆ of the lookup table to an output X of the lookup table as selected by the four input signals F0-F3.

FIG. 3 is a schematic diagram of another embodiment of a lookup table. In this embodiment, the lookup table is implemented using four memory cells 700 ₁-700 ₄ and a two-input decoding multiplexer 200 with two input signals, F0 and F1. The two-input decoding multiplexer 200 is shown in detail as being implemented by a hierarchy of pass transistors which propagate the value stored in the selected memory cell to the output X of the logic element. In FIG. 3, the memory cells may be implemented as shown in FIG. 1.

The above architecture was later augmented to enhance the functionality of the lookup tables. U.S. Pat. No. 5,343,406 to Freeman et al., incorporated herein by reference, describes how additional circuitry can enable lookup tables to behave as random access memories (RAMs) which can be both read and written after configuration of the logic device. When the option of allowing the user to write data to memory cells is available, there also must be provision for entering the user's data into these memory cells and reading from the memory cells. This capability is provided by including two means for accessing each dual function memory cell, one which is used to supply the configuration bitstream from off the chip, and another which is used during operation to storevalues from signals that are routed from the interconnect lines of the FPGA. FIG. 4 shows the memory cell architecture described in U.S. Pat. No. 5,343,406 which allows memory cell 750 to be programmed both during and after configuration. During configuration, memory cell 750 is programmed using the same process for programming the memory cell of FIG. 1.

After configuration, memory cell 750 is programmed differently. A value to be written to memory cell 750 is applied through the interconnect structure of the FPGA to the second data line 705, and then the corresponding write-strobe line WS for the memory cell is pulsed. This pulse latches the value on line 705 into memory cell 750. Like the lookup table of FIG. 2 which uses a series of memory cells from FIG. 1, a series of memory cells from FIG. 4 are combinable into a lookup table.

FIG. 5 is a block diagram showing a four-input lookup table with synchronous write capability. There is a write strobe generator 504 which receives a clock signal, CK, and a write enable signal, WE, and creates a single write strobe signal, WS, for the lookup table. To write a value to a desired memory cell, say 750 ₅, the value is applied on line D_(in) and the address of the desired memory cell 750 ₅ is applied to the input lines F0-F3 of demultiplexer 500. The value then is latched into the desired memory cell 750 ₅ by pulsing the write strobe. Conversely, to read a value stored in a different desired memory cell 750 ₃, the address of the memory cell 750 ₃ is applied to the input lines F0-F3 of decoding multiplexer 200 (without pulsing the write strobe), as was described with reference to FIGS. 2 and 3.

FIG. 6 is a schematic illustration of a two-input lookup table with synchronous write capability. FIG. 6 includes four memory cells 750 ₁ through 750 ₄. Detail of demultiplexer 500 and multiplexer 200 is shown in FIG. 6.

The implementation and operation of other logic array devices are described in “The Programmable Logic Data Book,” pages 4-1 to 4-372, copyright 1996 by Xilinx, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. This portion of “The Programmable Logic Data Book” is incorporated herein by reference.

Because a 4-input lookup table is only capable of storing 16-bits of data, it would be desirable to have an architecture that enables a plurality of lookup tables to be combined to form larger random access memories (RAMs) of selectable sizes. It would also be desirable if this architecture would enable dual-port RAMs of selectable sizes. It would further be desirable if this architecture did not significantly increase the complexity of the configurable logic elements (CLEs) in the FPGA.

One or more 4-input lookup tables, such as those illustrated in FIGS. 2 and 5, are typically used to implement combinatorial function generators in a configuration logic element (CLE). Some CLEs include a function generator to select between the outputs of two 4-input lookup tables in order to enable the CLE to implement any 5-input function. One such CLE, implemented in the Xilinx XC4000-Series FPGAs, is described in pages 4-11 through 4-23 of the Xilinx 1996 Data Book entitled “The Programmable Logic Data Book”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. The function generator can be replaced by a 2-to-1 multiplexer, with a signal selecting between the outputs of the two 4-input lookup tables, as disclosed in U.S. Pat. No. 5,349,250 entitled “Logic Structure and Circuit for Fast Carry” by Bernard J. New. Replacing the function generator with a 2-to-1 multiplexer still provides any function of up to five inputs and reduces the silicon area required to implement a the function generator. An FPGA using two 4-input lookup tables and a 2-to-1 multiplexer to implement a five input function generator is the XC5200™ family of products from Xilinx, Inc. The XC5200 CLE is described in pages 4-188 through 4-190 of the Xilinx 1996 Data Book.

A configurable logic block (CLB) capable of generating 6-input functions is described as implemented in the VIRTEX™ FPGAs from Xilinx Inc. This CLB includes two CLE slices, and is described in “The Programmable Logic Data Book 1999” pages 3-1 to 3-60, copyright 1999 by Xilinx, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.

It would be desirable to have a CLE structure that is capable of efficiently implementing functions larger than 6-input functions. It would further be desirable if this CLE structure is easily expandable, without significantly increasing the complexity of the CLE structure.

SUMMARY OF THE INVENTION

The present invention provides means and method for programming a configurable logic element so that the logic element can implement any one of a shift register and a combinatorial logic function using a lookup table. In one embodiment, the invention further provides for implementing a random access memory in this same logic element. The lookup table includes a plurality of memory cells which are connected in series so that an output of a first memory cell is configurable as an input to a second memory cell of the same lookup table. Further, by connecting shift registers of plural logic elements in series, larger shift registers can be built from smaller shift registers. Previous architectures built n-bit shift registers out of n flip flops connected in series, thereby wasting interconnect resources and logic while achieving mediocre performance.

In one mode, the memory cells which store the lookup table values are used as registers in a shift chain. When the logic element is in shift register mode, the Data-in value is shifted into the first cell and the value in each memory cell is shifted to the next cell. When the logic element is in random access memory mode, the Data-in value is written to a cell addressed by F3-F0, as discussed above. When the logic element is in pure lookup table mode, no value can be written after configuration and the logic element continues to generate the function loaded in during configuration.

According to another aspect of the invention, shift registers formed in a single lookup table can be cascaded together through cascade multiplexers to form larger shift registers. Each cascade multiplexer receives two input signals, the output signal from the last memory cell in a previous lookup table, and an input signal from the interconnect structure (or other selectable source). The output signal from the cascade multiplexer provides the input signal to the first memory cell in the next lookup table.

According to yet another aspect of the invention, a hierarchy of multiplexers is provided to generate functions of more inputs than the lookup table can handle. For example, a lookup table having 16 memory cells can generate functions of four input signals. By combining the outputs of two lookup tables in a multiplexer (F5) controlled by a fifth input signal, any function of five input signals can be generated. Using a sixth signal to select between the outputs of two such F5 multiplexers allows any function of six input signals to be generated, and so forth. In one embodiment, a configurable logic block (CLB) includes four slices, each having two four-input lookup tables (a total of eight lookup tables). The multiplexer hierarchy allows for all functions of eight input signals to be generated by selecting the output signal of one of the 16 lookup tables in a pair of CLBs. In addition to the eight lookup tables that generate functions of four input signals, the CLB includes four F5 multiplexers, where each F5 multiplexer receives input signals from two lookup tables and can generate all functions of five input signals when the two lookup tables receive the same four input signals and the F5 multiplexer is controlled by the fifth input signal. The CLB also includes two F6 multiplexers where each F6 multiplexer receives input signals from two of the F5 multiplexers. The CLB further includes an F7 multiplexer which receives the two F6 signals. The CLB also includes an F8 multiplexer which receives the F7 multiplexer output signal and an F7 multiplexer output signal from an adjacent CLB.

In one embodiment, this hierarchy of eight multiplexers is controlled by the same lines that provide shift register input signals. In this embodiment, the eight lookup tables are paired into 4 slices so that the downstream lookup table in each slice receives a shift register input signal on the line that also controls the F5 multiplexer for the slice. The upstream lookup table of the slice receives a shift register input signal on the line that controls an F6, F7 or F8 multiplexer. This arrangement is advantageous because the structure can be configured as a variable length shift register, where the line carrying the most upstream signal is used for loading shift register data and the more downstream lines all control multiplexers.

In accordance with another embodiment of the present invention, the plurality of function generators (lookup tables) present in the CLB are configured to form a random access memory (RAM). The width and depth of the RAM are selectable by controlling the routing of signals within the CLE slices. The hierarchy of multiplexers (e.g., the F5, F6, F7 multiplexers) are used to selectively route read data values from the lookup tables.

Another set of multiplexers is used to selectively route write data values to the lookup tables. These multiplexers can be configured to provide a single write data value to all of the lookup tables to form a deep RAM. Alternatively, these multiplexers can be configured to provide one write data value to half of the lookup tables, and another write data value to the other half of the lookup tables. This pattern repeats down to the level where these multiplexers can be configured to provide a different write data value to each of the lookup tables. Advantageously, each of the CLE slices includes the same multiplexer pattern, and each lookup table is accompanied by a corresponding multiplexer.

A write control circuit is also provided in each CLE slice to provide write enable signals to the lookup tables in the CLE slice. Each write control circuit generates the write enable signals in response to a plurality of write control signals received from various CLE slices. This advantageously enables the generation of many different patterns of write enable signals. Advantageously, each of the CLE slices includes an identical write control circuit.

Dedicated routing resources are provided to enable read and write addresses to be provided to the CLE slices in a manner that enables the CLB to be operated as a dual-port RAM having selectable width and depth.

The present invention will be more fully understood in view of the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of a first prior art memory cell architecture used in lookup tables in FPGAs where a value of the memory cell is stored during configuration.

FIG. 2 is a block diagram of a prior art programmable 4-input look-up table implemented by a sixteen-to-one decoding multiplexer and a series of sixteen memory cells.

FIG. 3 is an expanded view of a schematic illustration of a prior art two-input lookup table and a decoding multiplexer implemented by a hierarchy of pass gates.

FIG. 4 is a schematic illustration of a second prior art memory cell architecture used in lookup tables where the value of the memory cell is stored at configuration and remains dynamically readable and writable after configuration.

FIG. 5 is a block diagram of a prior art logic element that is configurable to implement either a sixteen-by-one random access memory or a four-input lookup table.

FIG. 6 is a schematic illustration of a prior art logic element that is configurable to implement either a four-bit random access memory or a two-input lookup table.

FIG. 7 is a schematic illustration of a memory cell architecture according to the present invention which can alternatively be configured as a shift register or a lookup table.

FIGS. 7A and 7B are waveform diagrams showing non-overlapping signals Phi1 and Phi2 which cause a bit value to shift from a preceding memory cell into the current memory cell when Phi2 is asserted.

FIG. 8 is a block diagram of a logic element according to the invention that can implement either a four-input lookup table or a 16-bit shift register.

FIG. 9 is a circuit diagram of a logic element according to the invention that can implement either a 2-input lookup table or a 4-bit shift register, where the mode of the logic element controls the operation of the control logic, and may be stored in configuration memory.

FIG. 10 is a schematic illustration of a memory cell for implementing any of a lookup table, a shift register, or a RAM.

FIG. 11 is a block diagram of a logic element that is configurable to implement any one of a four-input lookup table, a sixteen-bit shift register, and a sixteen-bit random access memory.

FIG. 12 is a schematic diagram of a logic element according to the present invention that is configurable to implement any one of a two-input lookup table, a four-bit shift register, and a four-bit random access memory.

FIG. 13 comprising FIGS. 13A through 13H shows waveform diagrams of the operation of the logic element when configured in shift-register mode.

FIG. 14 is a block diagram of a logic element which includes both a shift register and a flip-flop.

FIG. 15 is a block diagram of an FPGA.

FIG. 16 shows a 64-bit variable length shift register formed by combining structures such as shown in FIG. 8.

FIG. 17 shows a 64-bit variable length shift register formed using an architecture with an advantageous modification to the structure of FIG. 8.

FIG. 18 shows a logic slice structure from which the 64-bit variable length shift register of FIG. 17 can be formed.

FIG. 19 shows a layout of wiring for cascading adjacent lookup table slices by which interiors of adjacent lookup table slices can be identically laid out.

FIG. 20 shows more detail of the structure of FIG. 19, illustrating the lookup table structures.

FIG. 21 is a schematic diagram of a CLE slice S0 in accordance with one embodiment of the present invention.

FIG. 22 is a block diagram illustrating a CLB that includes four CLE slices S0-S3, each of which is identical to the CLE slice S0 of FIG. 21.

FIG. 23 is a block diagram of a CLB in accordance with another embodiment of the present invention.

FIG. 24 is a block diagram of a CLB in accordance with yet another embodiment of the present invention.

FIG. 25 is a block diagram illustrating selected multiplexers in the CLE slice of FIG. 21, as well as the associated function generators.

FIG. 26 is a circuit diagram of the write control circuit of the CLE slice of FIG. 21 in accordance with one embodiment of the present invention.

FIG. 27 is a block diagram illustrating the write control circuits in the CLE slices of FIG. 22 in accordance with one embodiment of the present invention.

FIG. 28 is a block diagram illustrating the routing of the address signals to the function generators in the CLE slices of FIG. 22.

DETAILED DESCRIPTION

With an increase in logic gate density, a shift register can now be implemented as one element of a larger user-configurable integrated circuit logic array. In a first embodiment of the present invention, a logic element is configurable to implement both an n-bit shift register and a (log₂ n)-input lookup table. FIG. 7 shows a schematic illustration of a memory cell 770 ₂ of the logic element architecture according to the present invention which, when configured to be in shift register mode, advantageously enables a value to be shifted from a preceding memory cell 770 ₁ into the memory cell 770 ₂. Memory cell 770 ₂ includes a pass transistor 706. The configuration value is written into memory cell 770 ₂ by pulsing configuration control line 702 of transistor 706, while applying the configuration value to the data line 704.

The output of memory cell 770 ₂ is programmably connected to the input of a next memory cell 770 ₃ by pass transistors 720 ₂, inverter 726 ₂, and a next pass transistor 708 ₃ not shown in FIG. 7. As shown by the timing diagrams in FIGS. 7A and 7B, during most of each cycle the clocking signal Phi1 on output control line 724 remains high, and thus the output signal 734 ₂ of memory cell 770 ₂ is applied through inverter 726 ₂ to shift input line 714 ₂ leading to the next memory cell 770 ₃. When Phi1 goes low at time t1, pass transistor 720 ₂ is turned off. Inverter 726 ₂ continues for a short time to hold as an output signal the logic level previously asserted by memory cell 770 ₂. In this way, the combination of transistor 720 ₂ and inverter 726 ₂ serves as a temporary latch. When a second clocking signal, Phi2, is asserted at time t2 on input control line 716, inverter 701 receives both the output of inverter 703 of memory cell 770 ₂ and the output of inverter 726 ₁ of the previous memory cell 770 ₁. Each inverter 726 is designed to overpower the inverter 703 so that values can be shifted between adjacent memory cells. Therefore, the current value stored in memory cell 770 ₂ is overwritten by the output of the previous memory cell 770 ₁. When Phi2 returns low at time t3, memory cell 770 ₂ is once again latched, holding its current value independent of changes in shift input line 714 ₁. At time t4, Phi1 goes high, thus applying the new value to inverter 726 ₂. Thus in one clock cycle, a bit shifts one cell. In contrast, if Phi1 and Phi2 mistakenly overlapped, the value of the output 734 of each memory cell 770 would propagate from preceding memory cell 700, through memory cell 770 ₂ to the next memory cell 770 ₃. This would not produce the desired single bit shift. However, by using non-overlapping two-phase clocking, as shown in FIGS. 7A and 7B, the memory cells shift one bit per cycle of Phi1 and Phi2.

FIG. 8 shows a logic element which implements a 16-bit shift register and 4-input lookup table according to a first embodiment of the invention. For simplicity, in FIG. 8 the structures within memory cells 770 of FIG. 7 have not been explicitly illustrated.

In FIG. 8, when in shift register mode, a first memory cell 770 ₁ of the memory is programmed with an initial value. The memory cell's value may be over written with a new value by applying the new value to the Din terminal of the first memory cell 770 ₁ and strobing the clock line, CK. The strobing of CK in turn invokes the two-phase clocking cycle of FIGS. 7A and 7B. As data is moved synchronously from left to right in the shift register, i.e., from the first memory cell 700 ₁ to a last memory cell 700 ₁₆, the logic element can continue to act as a lookup table though the function changes with every clock cycle. As in the prior art lookup tables, the decoding multiplexer 200 outputs on output line X the contents of the memory cell selected by the user inputs, i.e., F0-F3.

FIG. 9 shows a structure for implementing a 2-input lookup table or a 4-bit shift register, and shows internal structure of multiplexer 200 and memory cells 770 ₁ through 770 ₄. FIG. 9 is oriented on the page the same way as FIG. 8, and thus assists in understanding the relationship between the elements that make up the lookup table/shift register embodiment.

In a second embodiment of the present invention, a logic element is configurable to implement an n-bit shift register, an n-bit random access memory, and a (log₂ n)-input lookup table. FIGS. 10-12 illustrate this embodiment. FIG. 10 illustrates the memory cell. The memory cell of FIG. 10 can be loaded from three different sources. During configuration, memory cell 790 ₂ is loaded by applying configuration data to line 704 and strobing control line 702 of transistor 706. When memory cell 790 ₂ is in shift register mode, it is loaded through transistor 708, as discussed above. When memory cell 790 ₂ is in RAM mode, it is loaded through demultiplexer 500 on line 705 ₂. Write strobe line WS is pulsed, turning on transistor 707, and thus applying a data signal to node 730.

FIG. 11 shows a logic element which implements any one of a 16-bit shift register, a 16-bit random access memory, and 4-input lookup table according to the second embodiment of the present invention. In this embodiment, a memory cell, say 790 ₅, of the lookup table is programmed with an initial value during configuration, as discussed above. Subsequently, the initial value may be replaced in either of two ways, depending on the mode of the logic element: shift or RAM.

When the lookup table including memory cells 790 is being used in RAM mode, each memory cell 790 receives its data input on RAM input line 705. To write to any memory cell 790, the write strobe line WS pulses, thereby driving the value of Din through demultiplexer 500 into the addressed memory cell via input line 730.

The operation of the logic element in each of these modes is controlled by control logic 1000. Control bits which specify whether the logic element is in RAM mode, shift mode, or neither are inputs to control logic unit 1000. Control logic unit 1000 also receives the user clock signal and the write enable signal. From these inputs, control logic unit 1000 outputs Phi1, Phi2 and write strobe signal WS to either shift data between memory cells, to write to a particular memory cell, or to leave the memory cell data untouched. When in shift register mode, as in FIG. 8, data is moved synchronously from left to right in the shift register, i.e., from the first memory cell 790 ₁ to a last memory cell 790 ₁₆, as described above, by invoking a two-phase clocking cycle when CK is strobed. On the other hand, when the logic element is configured as a random access memory (RAM), the addressing lines F0-F3 select one of the memory cells (790 ₁ through 790 ₁₆) to be written to and read from by using the demultiplexer 500 and the decoding multiplexer 200, respectively. When in shift register mode, the first memory cell 790 ₁ receives as its input the signal applied to line D_(in). When in RAM mode, memory cell 790 ₁ receives an input signal on line 705 ₁ from demultiplexer 500.

In RAM mode, to write to a given memory cell, say 700 ₅, the write enable line WE must be active. When the user clock signal CK is asserted in conjunction with the active WE signal, control logic unit 1000 generates a write strobe WS. When the write strobe WS is high, memory cell 700 ₅ addressed by address lines F0-F3 of the demultiplexer 500 receives the value from data input line D_(in). This value overwrites the previous contents of the memory cell 700 ₅. No other memory cells receive the value applied to D_(in) since they are not addressed and therefore separated from D_(in) by high impedance connections from the demultiplexer 500.

FIG. 12 is a schematic illustration which shows more detail of a logic element according to the second embodiment of the present invention. Collectively, demultiplexer 500, decoding multiplexer 200, pass transistors 708 and 720, inverters 726, and RAM mode pass transistors 707 form an interconnection network and are combined with memory cells (790 ₁ through 790 ₄) and control logic unit 1000 to implement the logic element according to the second embodiment. If the logic element of the second embodiment is not configured as a shift register, then the logic element acts as either a random access memory or a lookup table. In either non-shift register mode, Phi2 is maintained at a low level, deactivating pass transistors 708, thereby blocking data from one memory cell 790 _(i) from affecting the next memory cell 790 _(i+1). Also, in the non-shift register modes, Phi1 is maintained at a high logic level, thereby feeding the outputs of the memory cells (790 ₁ to 790 ₄) through to the decoding multiplexer 200. As before, the output of the logic element is selected by the decoding multiplexer 200 according to the user inputs F0 and F1.

When the logic element of FIG. 12 is configured as a shift register, the RAM mode pass transistors 707 are turned off because WS is held low, isolating the memory cells from the outputs of demultiplexer 500. Memory cell 790 ₁ is programmably connected to D_(in) through transistor 708 ₁. To shift values, control logic unit 1000 produces control signals Phi1 and Phi2, triggered while the write enable signal is active by a rising edge of the User Clock signal CK applied to control logic unit 1000 such that values are shifted from one memory cell to next memory cell, i.e., from memory cell 790 _(i−1) to memory cell 790 _(i), and from memory cell 790 ₁ to memory cell 790 _(i+1). When control logic unit 1000 receives a rising edge of the user clock signal, control logic unit 1000 first pulls Phi1 low, then pulses Phi2 high long enough to overwrite the contents of the memory cells (790 ₁ to 790 ₄), and lastly reasserts Phi1 after Phi2 has fallen. It is important for extremely low clocking frequencies that Phi2 be only a pulse since Phi1 must be off while Phi2 is on. To accomplish this, the control logic is designed so that Phi1 and Phi2 do not rely on the falling edge of the User Clock signal 1008, but rather are self-timed.

FIG. 13 comprising FIGS. 13A through 13H are waveform diagrams of the operation of the logic element of FIG. 12. When the logic element of FIG. 12 is configured in shift-register mode, setting F1 to 1 and F0 to 0 makes it function as a three-bit shift register. As shown in FIG. 13E, the input, D_(in), to the three-bit shift register is maintained continuously at a high logic level throughout the example. Upon receiving a rising edge 1104 of a first user clock pulse 1108, control logic unit 1000 pulls Phi1 to a low logic level, as shown in FIG. 13G, to deactivate pass transistors 720 (FIG. 12). After temporarily having isolated the outputs 734 ₁ through 734 ₄ of the memory cells (790 ₁ through 790 ₄) from inputs of inverters 726 ₁ through 726 ₄, the control logic unit 1000 asserts Phi2, which propagates outputs of inverters 726 ₁ through 726 ₄ to their corresponding next memory cells, i.e., memory cells 790 ₂ through 790 ₄. When Phi2 is asserted, the value on D_(in) is written to first memory cell 790 ₁. The non-overlapping Phi2 pulse is shown in FIG. 13F. As shown in FIG. 13D, the value stored in first memory cell 790 ₁ (corresponding to 734 ₁) changes shortly after Phi2 is asserted. This change is indicated by reference 1112. The new value of output 734 ₁ of the first memory cell 790 ₁ does not affect the second memory cell 790 ₂ (corresponding to 734 ₂) because Phi1 is temporarily inactive. After asserting Phi2 long enough for the memory cells (790 ₁ to 790 ₄) to reach their new states, Phi2 is lowered, thereby latching the data values. Only after Phi2 has been lowered does control logic unit 1000 raise Phi1.

On receiving the rising edge of Phi1, the values of outputs 734 ₁ through 734 ₄ again pass through pass transistors 720 ₁ through 720 ₄. Reference numeral 1116 shows that the change in the output X of the three-bit shift register is synchronized with the rising edge of Phi1. As seen in FIGS. 13G and 13H, the reassertion of Phi1 and the lowering of the User Clock are independent, thus logic designers need not depend on exact timing relationships between these two edges. Of course, Phi1 must be reasserted before the inputs of inverters 726 ₁ through 726 ₄ float to an invalid voltage.

FIG. 14 is a block diagram of a logic element which includes both a logic element 1200 and a flip-flop 1204. The purpose of the flip-flop is to improve the clock-to-out delay of the output of the logic element 1200. This is simple and efficient in Xilinx FPGAs because function generators are historically paired with flip-flops in Xilinx logic elements. Further, when an n-bit, synchronous shift register is required, the logic element can be configured so that the shift register 1200 is an (n−1)-bit shift register and flip-flop 1204 is the final register of the n-bit shift register. When configured in this alternative fashion, the final bit XQ is available upon the rising edge 1104 of the User Clock pulse 1108, rather than on the rising edge 1116 of Phi1. This provides a faster clock-to-out time for the overall n-bit shift register.

By configuring the logic element to route XQ back to D_(in), the present invention can also perform circular shifts.

As discussed above (FIGS. 13A-13H), a shift register having fewer stages than the number of memory cells in a lookup table can be formed by directing a bit other than the last bit to output terminal X. Lookup tables likewise may be cascaded to create shift registers of a greater size than supported by a single lookup table. For example, it is possible to create a 20-bit shift register in a logic array composed of 16-bit lookup tables by cascading two logic elements. A first full 16-bit shift register 1200 and a second full 16-bit shift register 1200 combine to produce a 32-bit shift register. Thus, to achieve a 20-bit shift register, user input lines F0-F3 of the first logic element are set to 1111 and user input lines F0-F3 of the second logic element are 0011, i.e., the second 16-bit shift register 1200 is programmed to pass the output of the fourth memory cell 790 ₄, which is the final output of the 20-bit shift register. Additionally, in order to improve the clock-to-out delay of the cascaded shift registers, an alternate embodiment uses a first full 16-bit shift register 1200 addressed to 1111, a second full 16-bit shift register 1200 addressed to 0010 and the flip-flop 1204. The output, X, of the second shift register feeds the input of flip-flop 1204 of the second shift register. If desired, the flip-flops 1204 can also be used to extend the number bits that can be shifted within a logic element. Fully utilizing both 16-bit shift registers 1200 and their flip-flops 1204, cascaded shift registers can be built which are 17-bit, 34-bit, 51-bit, etc.

The novel shift register logic element is typically implemented in an FPGA such as the FPGA of FIG. 15 having logic blocks 101, each comprising a portion of an interconnect structure and a logic element. The FPGA of FIG. 15 is further discussed by Tavana et al. in the application Ser. No. 08/618,445 incorporated herein by reference.

FIG. 16 shows a 64-bit variable length shift register formed by combining structures such as shown in FIG. 8. Variable length shift registers are desired when building FIFOs (first-in-first-out storage devices).

Conventional FIFOs are commonly composed of a block of RAM addressed by READ and WRITE pointers which each increment through the block and cycle to the bottom upon reaching the top. When a word is written (pushed) into the FIFO, it is written to the address pointed to by the WRITE pointer, and the WRITE pointer is then incremented to point to the next address. When a word is read (popped) from the FIFO, it is taken from the address pointed to by the READ pointer and the READ pointer is incremented to the next address. Thus the data in a RAM based FIFO are never shifted. Rather, the READ and WRITE pointers are incremented independently.

In the present case using a shift register, whenever a WRITE command is received, data are always written to one location in a shift register and all other data are shifted one step through the shift register. In response to a WRITE command, a READ pointer is incremented. In response to a READ command, the READ pointer is decremented. There is no WRITE pointer. (The READ address represents the end of the string of stored data.) Such a shift register can be used to implement a variable length FIFO. If a shift register FIFO is desired that is no more than 16 words deep, then such a FIFO can be built in an FPGA using only one lookup table configured as a shift register for each bit of the word to be stored. If a FIFO is desired that can store more than 16 words, a structure such as shown in FIG. 16 must be built for each bit of the word. For example, a 64-word FIFO with 8-bit words would require 8 of the structures shown in FIG. 16. The structure of FIG. 16 can store up to 64 bits, the DATA bits being written from the left on data input line Din and being read out on the line OUT.

However, because the architecture of FIG. 8 provides only a single output from each LUT, (outputs are labeled X and Y), it is necessary to duplicate the data, an upper bank being used to store data for writing to subsequent lookup tables, and a lower bank being used for providing the particular data bit that has been addressed during a READ operation. A long shift register requires that the last sequential bit (770 ₁₆) of each 16-bit shift register be shifted to the first bit of the subsequent shift register, and that every bit be addressable by the READ address applied to the LUT output multiplexers 200. (If the FIFO is nearly empty, the READ address points to a memory cell near the left of the picture, for example cell 770 ₁ of LUT-G of slice S63. If the FIFO is nearly full, the READ address points to a memory cell near the right of the picture, for example cell 770 ₁₆ of LUT-F of slice S64.) Data bits are routed from one slice to another using the general interconnect routing lines. (These lines are illustrated using dotted lines to indicate that they are programmably connectable and to distinguish from the routing lines that are part of the slice itself.)

Using the architecture of FIG. 8, five slices S1 through S5 are used. A slice includes two lookup tables LUT-F and LUT-G, each comprising 16 memory cells 770, through 770 ₁₆, a multiplexer 200-F or 200-G, four LUT input lines F1 through F4 or G1 through G4 and a LUT output line X or Y. The slice also includes a clocking structure 800 receiving write enable signal WE, clock input signal CK, and a shift control signal from, for example, a configuration memory cell. Clocking structure 800 generates two non-overlapping clocking signals Phi1 and Phi2, as discussed earlier (See FIGS. 7A and 7B). These clocking signals Phi1 and Phi2 operate to shift bits to the right in response to clock signal CK when the shift memory cell contains a logic 1 and when the write enable signal WE is logic 1. In order to provide that the last bit 770 ₁₆ of lookup table LUT-G of slice S61 is fed to lookup table LUT-F of slice S63, while simultaneously allowing an addressed bit to be read from any of four lookup tables (two in slice S63 and two in slice S64), it is necessary to duplicate three of the four lookup tables and to configure the lookup tables so that in one lookup table the last bit is always routed out through multiplexer 200-F or 200-G to the first bit of the next shift register, and in the duplicate lookup table, the addressed bit is read. Thus, the addressed bit is read from the addressed lookup tables LUT-G of slice S63, LUT-F of slice S63, LUT-G of slice S64, or LUT-F of slice S64 while the last bit of lookup table LUT-G of slice S61, LUT-F of slice S61, or LUT-G of slice S62 is shifted in to the first bit of lookup table LUT-F of slice S63, LUT-G of slice S64 of LUT-F of slice S64, respectively, regardless of which address is being read out. Since lookup table LUT-F of slice S64 is the last in the chain, it is not necessary to form a duplicate in lookup table LUT-F of slice S62. (Recall that the data stored in slice S61 is identical to the data stored in slice S63, and the data stored in LUT-G of slice S62 is identical to the data stored in LUT-G of slice S64.)

As another aspect of the particular architecture of FIG. 8, discussed by Young, Chaudhary, and Bauer in pending U.S. patent application Ser. No. 08/806,997 [docket X-277], the content of which is incorporated herein by reference, multiplexers are included for generating five (F5) and six (F6) input functions by combining the outputs of the four-input lookup tables LUT-F and LUT-G. But in that described embodiment, the same input signal that feeds the Din signal also serves as the control signal on the F5 multiplexer. Thus, it is not possible to use an address signal for controlling the F5 multiplexer when also using that signal for supplying data. Thus a fifth slice S65 is used. The LUT-F and LUT-G lookup tables and an F5 multiplexer of slice S65 are configured to implement a four-to-one multiplexer, the output signal from this multiplexer being the addressed bit.

FIG. 17 shows a 64-bit variable length shift register formed using an architecture with an advantageous modification to the structure of FIG. 8. By changing the architecture to add a two-to-one multiplexer to the data input of each shift register and feeding the output signal of the last memory cell of the previous shift register to that multiplexer (in addition to the signal from the interconnect structure that exists in FIG. 8), a variable length shift register can be formed using no more than half the number of lookup tables of FIG. 16. The structure of FIG. 17 is configured as a 64-bit variable length shift register, just as is the structure of FIG. 16. But since the structure of FIG. 17 includes multiplexers M71 and M72 as inputs to the respective lookup table shift registers, each lookup table has both a variable-tap output through multiplexer 200 and a fixed output from cell 770 ₁₆. This is advantageous for making a FIFO because each lookup table now has the two outputs required when cascading together logic elements to build a long variable-tap shift register, so no duplication of logic is required. And the READ address dynamically addresses one of the 64 memory cells via the four lookup table input signals and the F5 and F6 multiplexers. Note that using the shift input of the newly added multiplexer M71 or M72 allows the BY or BX input of the newly added multiplexer to be used for another function, in this case controlling an F5 or F6 multiplexer.

FIG. 18 shows a logic slice structure from which the 64-bit variable length shift register of FIG. 17 can be formed, and in particular shows connections of the F5 multiplexer and another multiplexer labeled FX. A preferred architecture combines four of these slices into one configurable logic block (CLB). The FX multiplexer can be an F6, F7, or F8 multiplexer, depending upon the position of the illustrated slice in the CLB, where an F6 multiplexer selects between outputs of two F5 multiplexers, an F7 multiplexer selects from two F6 multiplexers, and an F8 multiplexer selects from two F7 multiplexers. FIG. 18 illustrates that the BX input signal goes two places: to multiplexer M72 and to the control terminal of the F5 multiplexer. Similarly, the BY input signal goes to multiplexer M71 and to the control terminal of the FX multiplexer. Note that the input signals to the FX multiplexer are labeled FXin0 and FXin1. These input signals come from other F5 or FX multiplexers within the CLB, and they are most conveniently illustrated in FIG. 19. In a preferred embodiment, a logic slice structure such as that of FIG. 18 will include additional elements, for example flip flops, fast carry circuits, and routing structures (see, for example, U.S. Pat. Nos. 5,267,187 to Hsieh et al., and U.S. Pat. No. 5,349,250 to New, as well as U.S. patent application Ser. No. 08/806,997 referenced above). However, to avoid obscuring the present invention, these additional structures have not been shown here.

FIG. 19 shows a layout of wiring for cascading adjacent lookup table slices by which interiors of adjacent lookup table slices can be identically laid out and by which a single input line BX or BY can serve a function in an earlier architecture as well as a new function discussed here (so the new architecture discussed here can implement designs that have been implemented in the previous architecture illustrated in FIG. 16). FIG. 19 illustrates one configurable logic block (CLB) comprising four slices, each having two lookup tables (LUTs). Each slice is equivalent to that of FIG. 18. Whereas FIG. 18 shows one F5 multiplexer and one FX multiplexer (in addition to the two M71 and M72 multiplexers discussed earlier), FIG. 19 shows the different interconnections to the FX multiplexer in different parts of one CLB. These wide function multiplexers are now labeled F6, F7, and F8 to show the number of input signals they can provide all function of. Thus, the F8 multiplexer selects from the output signals of two F7 multiplexers and an F7 multiplexer selects from two F6 multiplexers and so on. The lookup tables themselves provide all functions of four input signals. Note that the F8 multiplexer receives one input signal from the F7 multiplexer of its own CLB and another input signal from the F7 multiplexer of an adjacent CLB. Note also that one CLB includes four F5 multiplexers, two F6 multiplexers, one F7 multiplexer, and one F8 multiplexer.

The novel and advantageous placement of these wide function multiplexers always allows the control signal BX or BY to serve the dual function of providing shift-in data and controlling a corresponding multiplexer. This is because only one of the BX or BY terminals will be used for shifting in data to a shift register, and the sharing is arranged so that the highest order multiplexer is placed at the beginning of the shift register for that length. In the case of a 64-bit shift register, two slices will be used (see FIG. 17). The address will be six bits long and will use two F5 multiplexers and one F6 multiplexer. Looking at FIG. 19, this can be accomplished in either the upper two slices S3 and S2 or in the lower two slices S1 and S0. In either case, data will be shifted in on line BY of slice S3 or S1, and multiplexer M71 of the slice will be set to receive the BY signal. The F7 or F8 multiplexer will not be used since the desired output signal is provided by the F6 multiplexer of slice S2 or S0. Thus there is no conflict that the line used for controlling the F7 or F8 multiplexer is used in this case as a data input line to the shift register.

If a 128-bit shift register is desired, the entire CLB of FIG. 19 will be used. Data will be shifted in on the BY line of slice S3 and the output signal will be taken from the F7 multiplexer. The F8 multiplexer will not be used. Thus, again, there is no conflict in the fact that the line used for controlling multiplexer F8 is used to provide data to the shift register. Similarly, if a 256-bit shift register is desired, two CLBs of the type shown in FIG. 19 will be used, data being shifted in to the upper of the two CLBs and the output signal taken from the F8 multiplexer of the lower CLB. So again there is no conflict. Knowing this relationship, architectures can be provided having longer patterns of multiplexers for providing larger functions. All this is possible because for n-input lookup tables we need (n−1) lines for controlling multiplexers and 1 line for shifting in data to a shift register. The (n−1) multiplexer control signals plus 1 data-in signal exactly match the n lines provided.

Shift registers of sizes other than powers of two can also be formed by combining the appropriate number of slices. For example, if a user wanted a 200-bit variable length shift register, this could be implemented in seven slices using 13 LUTs, seven F5 multiplexers, four F6 multiplexers, two F7 multiplexers, and one F8 multiplexer. The three LUTs not needed in the eight slices that feed the F8 multiplexer could be used for other functions. To avoid generating an erroneous output signal if one of the unused lookup tables is addressed, the control inputs for the F5 and F6 multiplexers associated with partially used slices are preferably tied to a constant value.

FIG. 20 shows more detail of the structure of FIG. 19, illustrating the lookup table structures and clocking structures discussed earlier. Since the additional details of FIG. 20 have been discussed earlier, they are not discussed again here.

FIG. 21 is a schematic diagram of CLE slice S0 in accordance with one embodiment of the present invention. CLE slice S0 includes G and F function generators 1001 and 1002, exclusive OR gates 1003-1004, D-Q flip flops 1005-1006, AND gates 1007-1008, write control logic 1009, multiplexers 1010-1031, inverter 1040, and multiplexers F5 and FX. Slice S0 includes shift register circuitry consistent with that described above. The shift input data (e.g., SHIFTIN or BY) is provided to G function generator 1001 by multiplexer 1010. Data is shifted out of G function generator 1001 to multiplexer 1016. Note that multiplexer 1016 is also coupled to the output terminals of multiplexers 1010 and 1012. Data is shifted into F function generator 1002 from multiplexer 1016. Data is then shifted out of F function generator 1002 as the SHIFTOUT signal. Write control circuit 1009 controls the writing of data values to G and F function generators 1001 and 1002. Multiplexers 1010-1031 are configured to control the routing of the various signals in slice S0.

F function generator 1002 can be configured to implement a 4-input lookup table that provides an output signal F′ that is any function of the input signals F4-F1. The output signal F′ is routed to an input terminal of multiplexer F5. G function generator 1001 can be configured to implement a 4-input lookup table that provides an output signal G′ that is any function of the input signals G4-G1. The output signal G′ is routed to another input terminal of multiplexer F5. Multiplexer F5 is controlled by the bypass signal BX (or BX#, which is the inverse of BX). By routing the signals F1-F4 to the four input terminals of the G function generator 1001, multiplexer F5 can be used to provide an output signal F5′ that can be any function of the five input signals F4-F1 and BX.

The output signal G′ is also routed to an input terminal of multiplexer 1025. In accordance with the described embodiment, multiplexer 1025 is configured to route the output signal G′ as the output signal Y.

Multiplexer FX is a 2-to-1 multiplexer having two input terminals coupled to receive the FXA and FXB input signals, which are provided by the general interconnect located outside of CLE slice S0. Multiplexer FX is controlled by the bypass signal BY (or BY#, which is the inverse of BY). As described in more detail below, multiplexer FX is capable of operating as any multiplexer wider than an F5 multiplexer (i.e., F6, F7, F8, F9, F10, etc.), depending on the configuration of the CLE slice in a larger CLB circuit. These wider multiplexers are capable of providing any function of greater numbers of input signals. Thus, an F6 multiplexer is capable of providing any function of up to six input signals, and an F10 multiplexer is capable of providing any function of up to ten input signals. In the CLB circuit described below in connection with FIG. 22, the largest FX multiplexer is an F8 multiplexer.

FIG. 22 is a block diagram illustrating a CLB 1100 that includes four CLE slices S0-S3, each of which is identical to the CLE slice S0 of FIG. 21. FIG. 22 only illustrates G and F function generators and multiplexers F5 and FX in each of CLE slices S0-S3. Multiplexers F5 and FX are labeled as multiplexers F5 _(N) and FX_(N) in CLE slice SN. For example, within CLE slice S2, multiplexers F5 and FX are labeled as multiplexers F5 ₂ and FX₂. Similarly, the control signals BX and BY are labeled as control signals BX_(N) and BY_(N) in CLE slice SN.

The output terminals of multiplexers F5 ₀ and F5 ₁ are connected to the input terminals of multiplexer FX₀ in CLE slice S0. As a result, multiplexer FX₀ is configured as an F6 multiplexer (i.e., a multiplexer capable of providing an output signal that is any function of six input signals). This F6 multiplexer is capable of providing an output signal that is any function of the four F/G input signals to CLE slices S0-S1 (note that the same four input signals are provided to each F and G function generator in CLE slices S0 and S1), the BX₀/BX₁ input signal (note that the same input signal is provided to control the F5 ₀ and F5 ₁ multiplexers), and the BY₀ input signal.

The output terminals of multiplexers F5 ₂ and F5 ₃ are connected to the input terminals of multiplexer FX₂ in CLE slice S2. As a result, multiplexer FX₂ is also configured as an F6 multiplexer. This F6 multiplexer is capable of providing an output signal that is any function of the four FIG input signals to CLE slices S2-S3 (note that the same four input signals are provided to each F and G function generator in CLE slices S2 and S3), the BX₂/BX₃ input signal (note that the same input signal is provided to control the F5 ₂ and F5 ₃ multiplexers), and the BY₂ input signal.

Because the F6 multiplexer has a total of 19 inputs, an F6 multiplexer can also be configured to provide some (but not all) functions of up to 19 input signals. For example, the F6 multiplexer can be used to implement an 8-to-1 multiplexer, which is a function of 11 input signals (i.e., 8 input signals+3 control signals).

The output terminals of F6 multiplexers FX₀ and FX₂ are connected to the input terminals of multiplexer FX₁ in CLE slice S1. As a result, multiplexer FX₁ is configured as an F7 multiplexer (i.e., a multiplexer capable of providing an output signal that is any function of seven input signals). This F7 multiplexer is capable of providing an output signal that is any function of the four F/G input signals to CLE slices S0-S3 (note that the same four input signals are provided to each F and G function generator in CLE slices S0-S3), the BX₀/BX₁/BX₂/BX₃ input signal (note that the same input signal is provided to control the F5 ₀, F5 ₁, F5 ₂, and F5 ₃ multiplexers), the BY₀/BY₂ input signal (note that the same input signal is provided to control the FX₀ and FX₂ multiplexers), and the BY₁ input signal, which is provided to control the FX₁ multiplexer.

Because the F7 multiplexer has a total of 39 inputs, an F7 multiplexer can also be configured to provide some (but not all) functions of up to 39 input signals. For example, the F7 multiplexer can be used to implement an 16-to-1 multiplexer, which is a function of 20 input signals (i.e., 16 input signals+4 control signals).

The output terminal of F7 multiplexer FX₁ is connected to an input terminal of multiplexer FX₃ in CLE slice S3. The other input terminal of multiplexer FX₃ is connected to an output terminal of an F7 multiplexer in an upper adjacent CLB (not shown). The F7 multiplexer in the upper adjacent CLB is configured in the same manner as multiplexer FX₁ in CLB 1100. Because multiplexer FX₃ is configured to receive input signals from two F7 multiplexers, multiplexer FX₃ functions as an F8 multiplexer (i.e., a multiplexer capable of providing an output signal that is any function of eight input signals).

Because the F8 multiplexer has a total of 79 inputs, an F8 multiplexer can also be configured to provide some (but not all) functions of up to 79 input signals. For example, the F8 multiplexer can be used to form a 32-to-1 multiplexer, which is a function of 37 input signals (i.e., 32 input signals+5 control signals). In addition, the F8 multiplexer can be used to form a 256-bit variable tap shift register. Note that the F8 multiplexer requires the use of 2 CLBS.

The output terminal of F7 multiplexer FX₁ is also connected to a lower adjacent CLB. More specifically, the output terminal of multiplexer FX₁ is connected to an input terminal corresponding to the upper input terminal of multiplexer FX₃.

CLB 1100 is connected to a plurality of identical CLBS 1100, thereby providing an array of CLBS that are capable of providing F5, F6, F7 and F8 functions. The structure of the F8 multiplexer extends across CLB boundaries in a regular manner. As a result, CLB 1100 can be connected to either the upper adjacent CLB or the lower adjacent CLB to implement an F8 multiplexer. This advantageously provides flexibility in the configuration of the resulting FPGA.

In addition, each of the CLE slices in the various CLBs has an identical logic (transistor) layout. This advantageously simplifies the configuration software of the resulting FPGA, as well as the physical layout of the CLB array on a silicon substrate.

The above-described CLB structure can be easily expanded to provide for arbitrarily large functions. As described above in connection with FIG. 22, an F8 multiplexer structure can be created with four CLE slices. By doubling the number of CLE slices per CLB, a multiplexer structure having an additional input can be implemented. Thus, an F9 multiplexer can be created with eight CLE slices per CLB, and an F10 multiplexer can be created with sixteen CLE slices per CLB.

FIG. 23 is a block diagram of a CLB 1200 in accordance with another embodiment of the present invention. CLB 1200 includes eight CLE slices identical to CLE slice S0. These slices S0-S7 are configured to provide a CLB array that is capable of providing an F9 multiplexer that can provide any function of up to nine input signals. CLE slices S0-S7 of FIG. 23 are illustrated in the same manner as CLE slices S0-S3 in FIG. 22.

In CLB 1200, multiplexers FX₀, FX₂, FX₄ and FX₆ are all configured as F6 multiplexers. More specifically, the input terminals of multiplexer FX₀ are connected to the output terminals of multiplexers F5 ₀ and F5 ₁. The input terminals of multiplexer FX₂ are connected to the output terminals of multiplexers F5 ₂ and F5 ₃. The input terminals of multiplexer FX₄ are connected to the output terminals of multiplexers F5 ₄ and F5 ₅. The input terminals of multiplexer FX₆ are connected to the output terminals of multiplexers F5 ₆ and F5 ₇.

Multiplexers FX₁ and FX₅ are configured as F7 multiplexers. More specifically, the input terminals of multiplexer FX1 are connected to the output terminals of F6 multiplexers FX₀ and FX₂. The input terminals of multiplexer FX₅ are connected to the output terminals of F6 multiplexers FX₄ and FX₆.

Multiplexer FX₃ is configured as an F8 multiplexer. More specifically, the input terminals of multiplexer FX₃ are connected to the output terminals of F7 multiplexers FX₁ and FX₅.

Finally, multiplexer FX₇ is configured as an F9 multiplexer. More specifically, one input terminal of multiplexer FX₇ is connected to the output terminal of F8 multiplexer FX₃. The other input terminal of multiplexer FX₇ is connected to the output terminal of an F8 multiplexer in an upper adjacent CLB (not shown). This F8 multiplexer is located in a CLE slice identical to CLE slice S3 of CLB 1200. Note that the output terminal of F8 multiplexer FX₃ in CLB 1200 is also routed to a lower adjacent CLB (not shown). More specifically, the output terminal of multiplexer FX₃ is connected to the input terminal of the F9 multiplexer in the lower adjacent CLB.

The structure of the F9 multiplexer extends across CLB boundaries. However, each of the CLE slices and each of the CLBs are identical. This advantageously simplifies the configuration software of the resulting FPGA, as well as the layout of the FPGA on silicon.

In FIG. 21, CLE slice 1100 is defined to include a pair of function generators 1001-1002 and a pair of multiplexers F5 and FX. However, this is not necessary. In another embodiment, each CLE slice includes a single function generator and a single multiplexer that corresponds with either multiplexer F5 or multiplexer FX. FIG. 24 is a block diagram of a CLB 1200 in accordance with such an embodiment. CLB 1200 includes eight CLE slices S0-S7, wherein each of the CLE slices S₀-S₇ is defined to include one function generator and a corresponding multiplexer. (The other elements of CLE slices S₀-S₇ are not shown for purposes of clarity.) Similar elements in FIGS. 22 and 24 are labeled with similar reference numbers. The CLB structures illustrated by FIGS. 22 and 24 are similar. However, in FIG. 24, each of the F5 and FX multiplexers receives input signals from the general interconnect structure, and does not receive input signals from within the CLE slice. Thus, each of CLE slices S₀-S₇ includes a multiplexer that receives a user-defined control signal (i.e., BX or BY) and input signals from outside the CLE slice. (Note that a user-defined signal, as used herein, is not a signal provided by a configuration memory cell, but rather from a signal routed by the user on the general interconnect structure.) These identical CLE slices S₀-S₇ can be cascaded as illustrated to form wide function multiplexers (e.g., F5, F6, F7, and F8 multiplexers).

Returning to CLB 1100 of FIG. 22, in accordance with another embodiment of the present invention, CLE slices S0-S3 are connected in a manner that enables the function generators F₀-F₃ and G₀-G₃ in these CLE slices to be selectively connected to form random access memories (RAMs) of various sizes. As described above, each of the CLE slices S0-S3 has an identical transistor layout, thereby simplifying the design and configuration software of the resulting FPGA. In the described embodiment, CLB 1100 includes four CLE slices S0-S3 that can be configured to form RAMs having dimensions of 128×1, 64×2, 64×1, 32×4, 32×2, 32×1, 16×8, 16×4, 16×2 and 16×1. In other embodiments, this CLB structure can be expanded to include other numbers of CLE slices. In these embodiments, RAMs having other dimensions can be implemented. The manner of expanding the described CLB structure to include other numbers of CLE slices will be apparent to one of ordinary skill in the art in view of the following disclosure.

As described above, each 4-input F and G function generator includes sixteen memory cells that can be accessed in response to four address signals. In the described example, each F function generator is addressed by four read address signals F1-F4 and four write address signals WF1-WF4. The read address signals F1-F4 are separate from the write address signals WF1-WF4 to enable dual port access to the F function generator. Each G function generator is similarly configured to be accessed in response to read address signals G1-G4 and write address signals WG1-WG4.

Read Operations

To read one of the sixteen data values stored in an F or G function generator, a read address F1-F4 or G1-G4 is applied to the function generator. In response, the F or G function generator provides a data value corresponding to the read address as an output signal F′ or G′.

In the described embodiment, multiplexers FX₀-FX₃ and F5 ₀-F5 ₃ of CLE slices S0-S3 are connected as described above in connection with FIG. 22. As described in more detail below, these multiplexers are used to route read data values from function generators F₀-F₄ and G₀-G₄ to an appropriate output terminal.

128×1

More specifically, to operate CLB 1100 as a 128×1 RAM, the 128 memory cells in the F₀-F₄ and G₀-G₄ function generators of CLE slices S0-S3 are used to store 128 data values. The F₀-F₄ and G₀-G₄ function generators are addressed by the same four read address signals (i.e., F1/G1, F2/G2, F3/G3, F4/G4) during a read operation. These four read address signals are hereinafter referred to as address signals A₁-A₄. A single bypass signal (i.e., BX₀/BX₁/BX₂/Bx₃) is used to control multiplexers F5 ₀, F5 ₁, F5 ₂, and F5 ₃, thereby selecting either the output signals of the F₀-F₃ function generators or the output signals of the G₀-G₃ function generators. The bypass signal BX₀/BX₁/BX₂/BX₃ is thereby used as a fifth address signal A₅. In the described embodiment, if the fifth address signal A₅ has a logic “1” value, then multiplexers F5 ₀, F5 ₁, F5 ₂, and F5 ₃ route the output signals of the F₀-F₃ function generators. Conversely, if the fifth address signal A₅ has a logic “0” value, then multiplexers F5 ₀, F5 ₂, F5 ₂, and F5 ₃ route the output signals of the G₀-G₃ function generators.

Another bypass signal (i.e., BY₀/BY₂) is used to control F6 multiplexers FX₀ and FX₂, thereby selecting either the output signals of the F5 ₀ and F5 ₂ multiplexers or the output signals of the F5 ₁ and F5 ₃ multiplexers. The bypass signal BY₀/BY₂ is thereby used as a sixth address signal A₆. In the described embodiment, if the sixth address signal A₆ has a logic “1” value, then multiplexers FX₀ and FX₂ route the output signals of the F5 ₀ and F5 ₂ multiplexers, respectively. Conversely, if the sixth address signal A₆ has a logic “0” value, then multiplexers FX₀ and FX₂ route the output signals of the F5 ₁ and F5 ₃ multiplexers, respectively.

Another bypass signal (i.e., BY₁) is used to control F7 multiplexer FX₁, thereby selecting either the output signal of F6 multiplexer FX₀ or the output signal of F6 multiplexer FX₂ as the read data output signal. The bypass signal BY₁ is thereby used as a seventh address signal A₇. In the described embodiment, if the seventh address signal A₇ has a logic “1” value, then multiplexer FX₁ routes the output signal of the FX₀ multiplexer as the read output data value. Conversely, if the seventh address signal A₇ has a logic “0” value, then multiplexer FX₁ routes the output signal of the FX₂ multiplexer as the read output data value.

As described in more detail below, the address signals A₅-A₇ are also used to address the 128×1 RAM during write operations. As also described in more detail below, the unused bypass signal BY₃ is used to provide a write data value to the 128×1 RAM during write operations.

64×2, 64×1

To operate CLB 1100 as a 64×2 RAM, the 64 memory cells in the F₀, G₀, F₁ and G₁ function generators of CLE slices S0 and S1 are used to store a first set of 64 data values, and the 64 memory cells in the F₂, G₂, F₃ and G₃ function generators of CLE slices S2 and S3 are used to store a second set of 64 data values. In general, one of the 64 data values in function generators F₀, G₀, F₁ and G₁ is read out through multiplexers F5 ₀, F5 ₁ and FX₀ as a first bit of the two bit output signal. Similarly, a corresponding one of the 64 data values in function generators F₂, G₂, F₃ and G₃ is read out through multiplexers F5 ₂, F5 ₃ and FX₂ as a second bit of the two bit output signal.

More specifically, the F₀-F₃ and G₀-G₃ function generators are addressed by the same four read address signals A₁-A₄ during a read operation. Multiplexers F5 ₀-F5 ₃ are controlled by the fifth address signal A₅ (i.e., BX₀/BX₁/BX₂/BX₃), such that these multiplexers select either the output signals of the F₀-F₃ function generators or the output signals of the G₀-G₃ function generators. F6 multiplexers FX₀ and FX₂ are controlled by the sixth address signal A₆ (i.e., BY₀/BY₂), such that these multiplexers select either the output signals of multiplexers F5 ₀ and F5 ₂ or the output signals of multiplexers F5 ₁ and F5 ₃. In this manner, F6 multiplexer FX₀ provides one bit of the read output signal, and F6 multiplexer FX₂ provides the other bit of the read output signal in the 64×2 RAM.

As described in more detail below, the address signals A₅-A₆ are also used to address the 64×2 RAM during write operations. As also described in more detail below, the unused bypass signals BY₁ and BY₃ are used to provide write data values to the 64×2 RAM.

A 64×1 RAM, which uses only CLE slices S0 and S1, is a subset of the 64×2 RAM, which uses CLE slices S0, S1, S2, and S3. The 64×1 RAM is accessed in the same manner as the 64×2 RAM. An independent 64×1 RAM can not be implemented in S2 and S3 because the write addresses of S2 and S3 are tied to S0 and S1.

32×4, 32×2, 32×1

To operate CLB 1100 as a 32×4 RAM, the 32 memory cells in the F₀ and G₀ function generators of CLE slice S0 are used to store a first set of 32 data values, the 32 memory cells in the F₁ and G₁ function generators of CLE slice S1 are used to store a second set of 32 data values, the 32 memory cells in the F₂ and G₂ function generators of CLE slice S2 are used to store a third set of 32 data values, and the 32 memory cells in the F₃ and G₃ function generators of CLE slice S3 are used to store a fourth set of 32 data values.

In general, one of the 32 data values in function generators F₀ and G₀ is read out through multiplexer F5 ₀ as a first bit of the four bit output signal. Similarly, a corresponding one of the 32 data values in function generators F₁ and G₁ is read out through multiplexer F5 ₁ as a second bit of the four bit output signal. A corresponding one of the 32 data values in function generators F₂ and G₂ is read out through multiplexer F5 ₂ as a third bit of the four bit output signal. Finally, a corresponding one of the 32 data values in function generators F₃ and G₃ is read out through multiplexer F5 ₃ as a fourth bit of the four bit output signal.

More specifically, the F₀-F₃ and G₀-G₃ function generators are addressed by the same four read address signals A₁-A₄ during a read operation. Multiplexers F5 ₀-F5 ₃ are controlled by the fifth address signal A₅ (i.e., BX₀/BX₁/BX₂/BX₃), such that these multiplexers select either the output signals of the F₀-F₃ function generators or the output signals of the G₀-G₃ function generators. In this manner, multiplexers F5 ₀-F5 ₃ provide the four bits of the read output signal in the 32×4 RAM.

As described in more detail below, the address signal A₅ is also used to address the 32×4 RAM during write operations. As also described in more detail below, the unused bypass signals BY₀-BY₃ are used to provide write data values to the 32×4 RAM.

A 32×2 RAM is a subset of the 32×4 RAM, which uses only CLE slices S0 and S1. Similarly, a 32×1 RAM is a subset of the 32×4 RAM, which uses only CLE slice S0. The 32×2 and 32×1 RAMs are accessed in the same manner as the 32×4 RAM.

16×8, 16×4, 16×2, 16×1

It is noted that CLB 1100 can be operated as a 16×8, 16×4, 16×2 or 16×1 RAM by using the data values read directly out of the lookup tables F0-F3 and G0-G3. In these RAMS, it is not necessary to use multiplexers F5 ₀-F5 ₃ and FX₀-FX₃ to select the read data values. As described in more detail below, in the 16×8, 16×4, 16×2 or 16×1 RAMs, the unused bypass signals BX₀-BX₃ and BY₀-BY₃ are used to provide up to eight write data values to the 16×8 RAM.

In the foregoing manner, read data values for 128×1, 64×2, 64×1, 32×4, 32×2, 32×1, 16×8, 16×4, 16×2 and 16×1 RAMs can be routed out of CLB 1100 through multiplexers F5 ₀-F5 ₃ and FX₀-FX₃.

Write Operations

In order to operate CLB 1100 as a 128×1, 64×2, 64×1, 32×4, 32×2, 32×1, 16×8, 16×4, 16×2 and 16×1 RAM, it is necessary to provide a mechanism for routing input data values to the function generators F₀-F₃ and G₀-G₃ in a manner consistent with the various RAM configurations. As described in more detail below, this mechanism is largely provided by multiplexers 1010 and 1016 of CLE slice S0 (FIG. 21).

In addition, it is necessary to provide a mechanism for providing write enable signals to the various function generators F₀-F₃ and G₀-G₃ in a manner consistent with the various RAM configurations. As described in more detail below, this mechanism is largely provided by write control logic 1009, along with multiplexers 1030-1031 and inverter 1040 (FIG. 21).

Write Data Routing

FIG. 25 is a block diagram illustrating the multiplexers corresponding with multiplexers 1010 and 1016 in CLE slices S0-S3, as well as function generators F₀-F₃ and G₀-G₃. These multiplexers are labeled with the reference numbers 1010 _(N) and 1016 _(N), where N is the number slice in which the multiplexers are located. For example, multiplexers 1010 and 1016 in CLE slice S2 are labeled with the reference numbers 1010 ₂ and 1016 ₂, respectively. Many elements of CLE slices S0-S3 are not shown for purposes of clarity. In addition, the SHIFTIN input signals to multiplexers 1010 ₀-1010 ₃ and the input signals from the G₀-G₃ function generators to multiplexers 1016 ₀-1016 ₃ are not shown in FIG. 25, as these signals are not material to the present embodiment.

Each of multiplexers 1010 ₀-1010 ₃ is coupled to receive a 24 corresponding one of alternate data input signals ALTDIG₀-ALTDIG₃ and a corresponding one of bypass signals BY₀-BY₃. Each of multiplexers 1016 ₀-1016 ₃ is coupled to receive an output signal from a corresponding one of multiplexers 1010 ₀-1010 ₃ and a corresponding one of bypass signals BX₀-BX₃. The output signals provided by multiplexers 1010 ₀-1010 ₃ are routed from CLE slices S0-S3 as data signals DIG₀-DIG₃, respectively. Data signal DIG₃ is routed to provide input data signals ALTDIG₂ and ALTDIG₁ in CLE slices S2 and S1. Data signal DIG₁ is routed to provide input data signal ALTDIG₀ in CLE slice S0.

The output signals of multiplexers 1010 ₀-1010 ₃ are also provided to G function generators G₀-G₃ as write data input signals DINY₀-DINY₃, respectively. The output signals of multiplexers 1016 ₀-1016 ₃ are provided to F function generators F₀-F₃ as write data input signals DINX₀-DINX₃, respectively.

Multiplexers 1010 ₀-1010 ₃ and 1016 ₀-1016 ₃ are controlled as follows to route write data values to function generators F₀-F₃ and G₀-G₃.

128×1

When CLB 1100 is to operate as a 128×1 RAM, multiplexers 1010 ₀-1010 ₃ and 1016 ₀-1016 ₃ are configured to route the bypass signal BY₃ to the data input terminals of function generators F₀-F₃ and G₀-G₃. As a result, DINY₃=DINX₃=DINY₂=DINX₂=DINY₁=DINX₁=DINY₀=DINX₀=BY₃. Note that the bypass signal BY₃ is routed from CLE slice S3 to CLE slices S2 and S1 as the data signal DIG₃. Similarly, the bypass signal BY₃ is routed from CLE slice S1 to CLE slice S0 as the data signal DIG₁. As described in more detail below, a write enable control signal will be applied to one of function generators F₀-F₃ and G₀-G₃, thereby enabling the write data input signal (BY₃) to be written to this write-enabled function generator. The generation of this write enable control signal is controlled by the bypass signals BX₀-BX₃ and BY₀-BY₂ (i.e., the bypass signals other than BY₃).

64×2, 64×1

When CLB 1100 is to operate as a 64×2 RAM, the bypass signal BY₁ operates as a first write data input signal, and the bypass signal BY₃ operates as a second write data input signal. More specifically, multiplexers 1010 ₀-1010 ₁ and 1016 ₀-1016 ₁ are configured to route the bypass signal BY₁ to the write data input terminals of function generators F₀-F₁ and G₀-G₁. As a result, DINY₁=DINX₁=DINY₀=DINX₀=BY₁. Similarly, multiplexers 1010 ₂-1010 ₃ and 1016 ₂-1016 ₃ are configured to route the bypass signal BY₃ to the write data input terminals of function generators F₂-F₃ and G₂-G₃. As a result, DINY₃=DINX₃=DINY₂=DINX₂=BY₃.

As described in more detail below, during a write operation, a first write enable control signal is applied to one of function generators F₀, F₁, G₀ and G₁, and a second write enable control signal is applied to a corresponding one of function generators F₂, F₃, G₂, and G₃. In response, the write input data signals (BY₁ and BY₃) are written to the two function generators receiving the first and second write enable control signals. As described in more detail below, these first and second write enable control signals are generated in response to the bypass signals BX₀-BX₃, BY₀ and BY₂ (i.e., the bypass signals not used as write data input signals).

When CLB 1100 is to operate as a 64×1 RAM, CLE slices S0 and S1 are configured in the same manner described above for the 64×2 RAM. Thus, bypass signal BY₁ is used as the write input data signal and the bypass signals BX₀-BX₁ and BY₀ are used to generate the required write enable signal. In the 64×1 RAM configuration, function generators F₂-F₃ and G₂-G₃ are free to perform other functions.

32×4, 32×2, 32×1

When CLB 1100 is to operate as a 32×4 RAM, the bypass signals BY₀-BY₃ operate as four write data input signals. Thus, multiplexers 1010 ₀-1010 ₃ are configured to route the bypass signals BY₀-BY₃ to function generators G₀-G₃, respectively. Similarly, multiplexers 1016 ₀-1016 ₃ are configured to route the bypass signals BY₀-BY₃ to function generators F₀-F₃, respectively. Thus, DINY₃=DINX₃=BY₃, DINY₂=DINX₂=BY₂, DINY₁=DINX₁=BY₁, and DINY₀=DINX₀=BY₀.

As described in more detail below, during a write operation, a set of four write enable control signals is applied to either function generators F₀-F₃ or to function generators G₀-G₃. In response, the write input data signals (BY₀-BY₃) are written to the four function generators receiving the write enable control signals. As described in more detail below, the set of four write enable control signals are generated in response to the bypass signals BX₀-BX₃ (i.e., the bypass signals not used as write data input signals).

When CLB 1100 is to operate as a 32×2 RAM, CLE slices S0 and S1 are configured in the same manner described above for the 32×4 RAM. Thus, bypass signals BY₀ and BY₁ are used as the write input data signal and the bypass signals BX₀-BX₁ are used to generate the required write enable signals. In the 32×2 RAM configuration, function generators F₂-F₃ and G₂-G₃ are free to perform other functions.

Similarly, when CLB 1100 is to operate as a 32×1 RAM, CLE slice S0 is configured in the same manner described above for the 32×4 RAM. Thus, bypass signal BY₀ is used as the write input data signal and the bypass signal BX₀ is used to generate the required write enable signals. In the 32×1 RAM configuration, function generators F₁-F₃ and G₁-G₃ are free to perform other functions.

In the foregoing manner, multiplexers 1010 ₀-1010 ₃ and 1016 ₀-1016 ₃ provide a structure that enables the flexible application of write data values to function generators F₀-F₃ and G₀-G₃. Advantageously, many variations are possible, even though each of the CLE slices S0-S3 has an identical transistor layout.

In the 128×1, 64×2, 32×4, and 16×8 RAMs, the write address terminals WF0-WF3 and WG0-WG3 of each of the function generators F0-F3 and G0-G3 are coupled to receive the A₁-A₄ address signals. This is because these configurations all have shared read and write addresses. However, these write address signals are only effective within the associated function generator if the write enable signal corresponding to the function generator is asserted low.

Write Enable Control Signals

The mechanism for generating the write enable control signals for the various RAMs will now be described. Within each CLE slice, a pair of write enable control signals are generated by write control circuit 1009 (FIG. 22). In the present description, the write control circuits in CLE slices S0-S3 are labeled as write control circuits 1009 ₀-1009 ₃, respectively.

FIG. 26 is a circuit diagram of write control circuit 1009 ₀ of CLE slice S0 in accordance with one embodiment of the present invention. Write control circuit 1009 ₀ includes NAND gates 2501-2502, multiplexers 2503-2504 and inverter 2505. If multiplexer 2503 is configured to route the SLICEWE0 signal, then multiplexer 2503 provides the SLICEWE0 signal to NAND gate 2502. If multiplexer 2504 is configured to pass the output signal provided by inverter 2505, then multiplexer 2504 provides the inverse of the SLICEWE0 signal (SLICEWE0#) to NAND gate 2501. Under these conditions, the SLICEWE0 signal is said to be ‘enabled’ within write control circuit 1009 ₀. (Note that if multiplexers 2503 and 2504 are configured to pass logic “1” values, then NAND gates 2501 and 2502 will receive these logic “1” values, thereby effectively disabling the SLICEWE0 signal).

Assuming that the SLICEWE0 signal is enabled in write control circuit 1009 ₀, NAND gate 2501 generates a write enable control signal WEG#₀ in response to the SLICEWE2 signal, the SLICEWE1 signal, and the SLICEWE0# signal. Similarly, NAND gate 2502 generates a write enable control signal WEF#₀ in response to the SLICEWE2 signal, the SLICEWE1 signal, and the SLICEWE0 signal. The WEG#₀ and WEF#₀ write control signals are provided to the write enable input terminals of function generators G₀ and F₀, respectively. When one of the WEG#₀ and WEF#₀ write control signals is asserted LOW, a write operation is enabled in the corresponding function generator G₀ or F₀. As described in more detail below, bypass output signals BYOUT and inverted bypass output signals BYINVOUT are generally provided as the SLICEWE2 and SLICEWE1 signals. The bypass output signals BXOUT are generally provided as the SLICEWE0 signals.

FIG. 27 is a block diagram illustrating the write control circuits 1009 ₀-1009 ₃ and function generators F₀-F₃, G₀-G₃ in CLE slices S0-S3 of CLB 1100 in accordance with the described embodiment. The other elements of CLE slices S0-S3 are not shown in FIG. 27 for purposes of clarity. Write control circuit 1009 ₀ is connected to receive bypass signals BY₁, BY₀, and BX₀. Write control circuit 1009 ₁ is connected to receive bypass signals BY₁, BY₀#, and BX₁. Write control circuit 1009 ₂ is connected to receive bypass signals BY₁#, BY₀, and BX₀. Write control circuit 1009 ₃ is connected to receive bypass signals BY₁#, BY₀#, and BX₁.

Referring to FIG. 21, it is noted that the BY and BY# bypass signals, which are provided as output signals at the BYOUT and BYINVOUT terminals, can be disabled (i.e., set at logic “1” values) by configuring multiplexers 1030 and 1031 in the appropriate manner. Conversely, these multiplexers and 1031 can be configured to enable the BY and BY# signals at the BYOUT and BYINVOUT output terminals.

128×1

The write control structure of CLB 1100 operates as lows. When CLB 1100 is to be operated as a 128×1 RAM, the ass signals BY₀-BY₁, BY₀#-BY₁# and BX₀-BX₁ provided to write control circuits 1009 ₀-1009 ₃ are all enabled. Bypass signals BX₀-BX₁ are identical, and correspond with the fifth address signal A₅. Bypass signal BY₀ corresponds with the sixth address signal A₅, and bypass signal BY₁ corresponds with the seventh address signal A₇. Table 1 below summarizes the manner in which write control circuits 1009 ₀-1009 ₃ assert the write enable signals WEG#₀-WEG#₃ and WEF#₀-WEF#₃ in response to the address signals A₇-A₅.

TABLE 1 A₇-A₅ WEG#₃ WEF#₃ WEG#₂ WEF#₂ WEG#₁ WEF#₁ WEG#₀ WEF#₀ 000 0 1 1 1 1 1 1 1 001 1 0 1 1 1 1 1 1 010 1 1 0 1 1 1 1 1 011 1 1 1 0 1 1 1 1 100 1 1 1 1 0 1 1 1 101 1 1 1 1 1 0 1 1 110 1 1 1 1 1 1 0 1 111 1 1 1 1 1 1 1 0

As shown in Table 1, a different one of the function generators F0-F3, G0-G3 is write-enabled for each instance of the address signals A₇-A₅. Thus, the addressing scheme of the write control structure corresponds with the addressing scheme of the read control structure described above.

64×2 or 64×1

When CLB 1100 is to be operated as a 64×2 or 64×1 RAM, bypass signals BY₀, BY₀#, and BX₀-BX₁ provided to write control circuits 1009 ₀-1009 ₃ are enabled. Bypass signals BY₁ BY₁# provided to write control circuits 1009 ₀-1009 ₃ are disabled (i.e., set to logic “1” values) by appropriately configuring the multiplexers 1030-1031 in CLE slice S1. As described above, bypass signal BY₁ is used as a write data value in this configuration. Bypass signals BX₀-BX₁ are identical, and correspond with the fifth address signal A₅. Bypass signal BY₀ corresponds with the sixth address signal A₆. Table 2 below summarizes the manner in which write control circuits 1009 ₀-1009 ₃ assert the write enable signals WEG#₀-WEG#₃ and WEF#₀-WEF#₃ in response to the address signals A₆-A₅.

TABLE 2 A₆-A₅ WEG#₃ WEF#₃ WEG#₂ WEF#₂ WEG#₁ WEF#₁ WEG#₀ WEF#₀ 00 0 1 1 1 0 1 1 1 01 1 0 1 1 1 0 1 1 10 1 1 0 1 1 1 0 1 11 1 1 1 0 1 1 1 0

As shown in Table 2, a different pair of the function generators F0-F3, G0-G3 is write-enabled for each instance of the address signals A₆-A₅. Thus, the addressing scheme of the write control structure corresponds with the addressing scheme of the read control structure described above.

32×4, 32×2 or 32×1

When CLB 1100 is to be operated as a 32×4, 32×2 or 32×1 RAM, the bypass signals BX₀-BX₁ provided to write control circuits 1009 ₀-1009 ₃ are enabled. Bypass signals BY₀-BY₁ and BY₀#-BY₁# provided to write control circuits 1009 ₀-1009 ₃ are disabled (i.e., set to logic “1” values) by appropriately configuring the multiplexers 1030 and 1031 in CLE slices S0-S3. As described above, bypass signals BY₁ and BY₀ are used as write data values in this configuration. Bypass signals BX₀-BX₁ are identical, and correspond with the fifth address signal A₅. Table 3 below summarizes the manner in which write control circuits 1009 ₀-1009 ₃ assert the write enable signals WEG#₀-WEG#₃ and WEF#₀-WEF#₃ in response to the address signal A₅.

TABLE 3 A₅ WEG#₃ WEF#₃ WEG#₂ WEF#₂ WEG#₁ WEF#₁ WEG#₀ WEF#₀ 0 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0

As shown in Table 3, a different set of four function generators is write-enabled for each instance of the address signal A₅. Thus, the addressing scheme of the write control structure corresponds with the addressing scheme of the read control structure described above.

In the foregoing manner, the write enable signals are provided to function generators F₀-F₃ and G₀-G₃. Advantageously, a wide variety of write enable signal patterns can be provided to the function generators F₀-F₃ and G₀-G₃ in the CLB 1100, with relatively little overhead. In addition, because the transistor layout of each of the CLE slices is identical, the layout and software configuration of the resulting FPGA is simplified.

The functionality of the bypass signals BX₀-BX₃ and BY₀-BY₃ in the 128×1, 64×2, 32×4 and 16×8 RAM embodiments is summarized below in Table 4.

TABLE 4 Signal 128 × 1 64 × 2 32 × 4 16 × 1 BY₃ DATA DATA DATA DATA BY₂ A₆ A₆ DATA DATA BY₁ A₇ DATA DATA DATA BY₀ A₆ A₆ DATA DATA BX₃ A₅ A₅ A₅ DATA BX₂ A₅ A₅ A₅ DATA BX₁ A₅ A₅ A₅ DATA BX₀ A₅ A₅ A₅ DATA

In accordance with yet another embodiment of the present invention, CLB 1100 can be operated as a dual-port RAM of various sizes. In the above-described single-port RAM embodiments, the address signals A₁-A₄ are provided to each of the function generators F₀-F₃ and G₀-G₃ used to implement the single-port RAM. The routing of address signals A₁-A₄ in the single-port embodiments is therefore straightforward. However, in the case of a dual-port implementation, the routing of the address signals A₁-A₄ becomes more complex.

FIG. 28 is a block diagram of CLB 1100, which illustrates the connections to the four address inputs of function generators F₀-F₃ and G₀-G₃ in accordance with one embodiment of the present invention. Address AA[4:1] is provided as a write address signal (i.e., WF0-WF3 or WG0-WG3) to function generators F₀, G₀, F₂ and G₂. Address AA[4:1] is also provided as a read address signal (i.e., F0-F3 or G0-G3) to function generators F₀ and G₀.

Address AB[4:1] is provided as a write address signal (i.e., WF0-WF3 or WG0-WG3) to function generators F₁, G₁, F₃ and G₃. Address AB[4:1] is also provided as a read address signal (i.e., F0-F3 or G0-G3) to function generators F₁ and G₁.

Address AC[4:1] is provided as a read address signal (i.e., F0-F3 or G0-G3) to function generators F₂ and G₂. Address AD[4:1] is provided as a read address signal (i.e., F0-F3 or G0-G3) to function generators F₃ and G₃.

Note that in the above-described single-port embodiments, AA[4:1]=AB[4:1]=AC[4:1]=AD[4:1]=A₄-A₁. However, in the dual-port embodiments addressing is implemented as follows.

64×1 Dual-Port

CLB 1100 can be configured to operate as a 64×1 dual-port RAM in the following manner. In general, function generators F₀-F₁ and G₀-G₁ are used to implement a write port of the dual-port memory, and function generators F₂-F₃ and G₂-G₃ are used to implement a read-only port of the dual-port memory. Note that data values can also be read from function generators F₀-F₁ and G₀-G₁, thereby making the write port a read/write port, if desired. Data values are written to the 64×1 dual-port memory as follows. The write control circuits 1009 ₀-1009 ₃ are configured in the manner described above for a 64×2 RAM array. As a result, write enable signals are provided to pairs of function generators as shown in Table 2. Data input multiplexers 1010 ₀-1010 ₃ and 1016 ₀-1016 ₃ are configured in the manner described above for a 64×2 RAM array. Thus, a single data signal is routed to both BY₃ and BY₁, and is thus provided to the data input terminal of each of the function generators F₀-F₃ and G₀-G₃.

The desired write address signals A₄-A₁ are applied to the write address terminals of function generators F₀-F₃ and G₀-G₃ as address signals AA[4:1] and AB[4:1]. As described above in connection with the 64×2 RAM, write operations will be enabled in one of function generators F₀-F₁ and G₀-G₁, and in a corresponding one of function generators F₂-F₃ and G₂-G₃. For example, a write operation may be enabled in function generators F₀ and F₂ (See, Table 2). As a result, the data written to CLB 1100 is stored in two locations, namely, at one location in function generators F₀-F₁ and G₀-G₁, and at a corresponding location in function generators F₂-F₃ and G₂-G₃.

Data can be read from the read-only port of 64×1 dual-port RAM as follows. The desired read address signals A₄-A₁ are applied to the read address terminals of function generators F₂-F₃ and G₂-G₃ as address signals AC[4:1] and AD[4:1]. As a result, read operations will be enabled in all four of these function generators F₂-F₃ and G₂-G₃ at the address location identified by the read address signals A₄-A₁. The wide function multiplexers F5 ₂, F5 ₃ and FX₂ are configured as described above in the 64×2 single-port RAM embodiment. These multiplexers F5 ₂, F5 ₃ and FX₂ are controlled to select the appropriate read output signal from function generators F₂-F₃ and G₂-G₃ in response to the address signals A₅ and A₆.

32×2, 31×1 Dual-Port RAM

CLB 1100 can be configured to operate as a 32×2 dual-port memory in the following manner. In general, function generators F₀-F₁ and G₀-G₁ and are used to implement a write port of the dual-port memory, and function generators F₂-F₃ and G₂-G₃ are used to implement a read-only port of the dual-port memory. Note that data values can also be read from function generators F₀-F₁ and G₀-G₁, thereby making the write port a read/write port, if desired. Data values are written to the 32×2 dual-port memory as follows. The write control circuits 1009 ₀-1009 ₃ are configured in the manner described above for a 32×4 RAM array. As a result, write enable signals are provided to sets of four function generators as shown in Table 3. Data input multiplexers 1010 ₀-1010 ₃ and 1016 ₀-1016 ₃ are configured in the manner described above for a 32×4 RAM array. A first data signal (BY₂/BY₀) is provided to the data input terminal of each of the function generators F₀, F₂ and G₀, and G₂. A second data signal (BY₃/BY₁) is provided to the data input terminal of each of the function generators F₁, F_(3 and G) ₁, and G₃.

The desired write address signals A₄-A₁ are applied to the write address terminals of function generators F₀-F₃ and G₀-G₃ as address signals AA[4:1] and AB[4:1]. As described above in connection with the 32×4 RAM, write operations will be enabled in one of the function generators in each of the CLE slices S₀-S₃. For example, write operations may be enabled at the address identified by write address A₄-A₁ in function generators F₀, F₁, F₂ and F₃ (or in function generators G₀, G₁, G₂ and G₃). (See, Table 3). As a result, the first data signal (BY₂/BY₀) written to CLB 1100 is stored in two locations, namely, at one location in function generators F₀ and G₀ and at a corresponding location in function generators F₂ and G₂. Similarly, the second data signal (BY₃/BY₁) written to CLB 1100 is stored in two locations, namely, at one location in function generators F₁ and G₁ and at a corresponding location in function generators F₃ and G₃.

Data can be read from the read-only port of 32×2 dual-port RAM as follows. The desired read address signals A₄-A₁ are applied to the read address terminals of function generators F₂-F₃ and G₂-G₃ as address signals AC[4:1] and AD[4:l]. As a result, read operations will be enabled in all four of these function generators F₂-F₃ and G₂-G₃ at the address location identified by the read address signals A₄-A₁. The wide function multiplexers F5 ₀-F5 ₃ are configured as described above in the 32×4 single-port RAM embodiment. Multiplexers F5 ₂ and F5 ₃ are controlled to select the appropriate read output signal from function generators F₂-F₃ and G₂-G₃ in response to the address signal A₅.

A 32×1 dual-port RAM can be implemented by using only half of the 32×2 dual-port RAM. For example, a 32×1 dual-port RAM can be implemented by using function generators F₀ and G₀ to form the write port, and function generators F₂ and G₂ to form the read-only port.

16×4, 16×2, 16×1 Dual-Port RAM

CLB 1100 be configured to operate as a 16×4 dual-port memory in the following manner. In general, function generators F₀-F₁ and G₀-G₁ and are used to implement a write port of the dual-port memory, and function generators F₂-F₃ and G₂-G₃ are used to implement a read-only port of the dual-port memory. Note that data values can also be read from function generators F₀-F₁ and G₀-G₁, thereby making the write port a read/write port, if desired. Data values are written to the 16×4 dual-port memory as follows. The write control circuits 1009 ₀-1009 ₃ are configured in the manner described above for a 16×8 RAM array. The input data values are routed through multiplexers 1010 ₀-1010 ₃ and 1016 ₀-1016 ₃ to function generators F₀-F₃ and G₀-G₃ as described above for a 16×8 RAM array. The desired write address signals A₄-A₁ are applied to the write address terminals of function generators F₀-F₃ and G₀-G₃ as address signals AA[4:1] and AB[4:1]. As described above in connection with the 16×8 RAM, write operations will be enabled in each of the function generators in CLE slices S₀-S₃. As a result, a first bit written to CLB 1100 is stored in two locations, namely, at one location in function generator F₀ and at a corresponding location in function generator F₂. Similarly, a second bit is stored at one location in function generator G₀ and at a corresponding location in function generator G₂. A third bit is stored at one location in function generator F₁ and at a corresponding location in function generator F₃. Finally, a fourth bit is stored in one location in function generator G₁ and a corresponding location in function generator G₃.

Data can be read from the read-only port of 16×4 dual-port RAM as follows. The desired read address signals A₄-A₁ are applied to the read address terminals of function generators F₂-F₃ and G₂-G₃ as address signals AC[4:1] and AD[4:1]. As a result, read operations will be enabled in all four of these function generators F₂-F₃ and G₂-G₃ at the address location identified by the read address signals A₄-A₁. As described above in the 16×8 single-port RAM embodiment, these four signals are routed directly from the function generators as read output signals.

A 16×2 or 16×1 dual-port RAM can be implemented by using only a half or a quarter, respectively, of the 16×8 dual-port RAM. For example, a 16×1 dual-port RAM can be implemented by using function generator F0 to form the write port, and function generator F₂ to form the read-only port.

Numerous modifications and variations of the present invention are possible in light of the above teachings. Although FIGS. 7 and 10 show a memory cell programmed through only one node of the latch, the invention can also be used with memory cells in which some data signals are inverted and applied to both nodes of the latch, or in which different control signals are applied to different nodes of the latch. Further, in FIG. 10 the three transistors 706, 708, and 707 can be implemented as a multiplexer receiving input signals on lines 704, 714, and 705. And transistors 706, 708, 707, and 720 can be replaced by transmission gates. While particular multiplexer and demultiplexer implementations are shown, the invention can use other implementations as well. And, of course, different structures and methods for generating signals such as Phi1, Phi2, and WS can be used with the invention. Further, although the above embodiments show a single multiplexer with a single output terminal for selecting one signal from a plurality of memory cells, other embodiments can select more than one memory cell from which to provide an output signal. And although FIGS. 19 and 20 show a CLB with lookup tables and multiplexers for generating functions of up to 8 input signals, other embodiments can use CLBs with more lookup tables and higher order multiplexers, for example CLBs with 16 or 32 lookup tables with F9 and F10 multiplexers. A lookup table can have fewer or more than the 16 memory cells shown For example, a 6-input lookup table would use 64 memory cells (configurable as a shift register) and the combining multiplexers would start with F7. Further, although the cascading aspect of the invention has been discussed in comparison to FIG. 8, this aspect also applies to structures with demultiplexing, such as shown in FIG. 11. More fundamentally, although the above invention has been described in connection with an FPGA, a shift register with cascade multiplexers can be formed in other structures than FPGAs, and formed not in connection with lookup tables.

It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described above. 

We claim:
 1. A configurable logic block (CLB) having a plurality configurable logic element (CLE) slices, wherein each of CLE slices comprises: a first function generator (F) having a first write data input terminal; a second function generator (G) having a second write data input terminal; a first multiplexer (1016) having an input terminal coupled to receive a first bypass signal (BX) and an output terminal coupled to the first write data terminal; and a second multiplexer (1010) having an input terminal coupled to receive a second bypass signal (BY), an alternate input terminal (ALTDIG) coupled to receive an alternate input signal, and an output terminal coupled to the second write data terminal, an input terminal of the first multiplexer, and an alternate output terminal (DIG).
 2. A configurable logic block (CLB) comprising: a first CLE slice (S0) having a first set of function generators (F₀,G₀) and a corresponding first set of multiplexers (1010, 1016) for providing write data values to the first set of function generators; a second CLE slice (S1) having a second set of function generators (F₁,G₁) and a corresponding second set of multiplexers for providing write data values to the second set of function generators, wherein the second set of multiplexers is coupled to the first set of multiplexers, thereby routing a write data value from the second CLE slice to the first CLE slice.
 3. The CLB of claim 2, wherein the first set of function generators comprises a first function generator and a second function generator, and the first set of multiplexers comprises a first multiplexer and a second multiplexer, wherein an output terminal of the first multiplexer is coupled to provide a write data value to the first function generator, and an output terminal of the second multiplexer is coupled to provide a write data value to the second function generator and to an input terminal of the first multiplexer.
 4. The CLB of claim 3, wherein the second set of function generators comprises a third function generator and a fourth function generator, and the second set of multiplexers comprises a third multiplexer and a fourth multiplexer, wherein an output terminal of the third multiplexer is coupled to provide a write data value to the third function generator, and an output terminal of the fourth multiplexer is coupled to provide a write data value to the fourth function generator and to an input terminal of the third multiplexer.
 5. The CLB of claim 4, further comprising a connection between the output terminal of the fourth multiplexer and an input terminal of the second multiplexer.
 6. The CLB of claim 2, wherein the CLE slices are identical.
 7. A configurable logic block (CLB) comprising: a first CLE slice (S0) having a first set of function generators (F₀,G₀) and a corresponding first write control circuit for providing write enable signals to the first set of function generators; a second CLE slice (S1) having a second set of function generators (F₁,G₁) and a corresponding second write control circuit for providing write enable signals to the second set of function generators, wherein the first write control circuit is coupled to receive an address signal from the second CLE slice.
 8. The CLB of claim 7, wherein the second write control circuit is coupled to receive an address signal from the first CLE slice.
 9. The CLB of claim 7, further comprising a third CLE slice (S2) having a third set of function generators (F₂,G₂) and a corresponding third write control circuit for providing write enable signals to the third set of function generators, wherein the third write control circuit is coupled to receive an address signal from the second CLE slice.
 10. The CLB of claim 7, wherein the first and second CLE slices are identical.
 11. The CLB of claim 9, wherein the first, second and third CLE slices are identical.
 12. The CLE of claim 9, further comprising a fourth CLE slice (S3) having a fourth set of function generators (F₃,G₃) and a corresponding fourth write control circuit for providing write enable signals to the fourth set of function generators, wherein the fourth write control circuit is coupled to receive address signals from the second CLE slice and the third CLE slice.
 13. The CLB of claim 12, wherein the first, second, third and fourth CLE slices are identical.
 14. A configurable logic block (CLB) comprising: a plurality of function generators, each having a write data input terminal and a read data output terminal; a first set of hierarchically connected multiplexers (F50-F53, FX0-FX3) configured to route data values from the read data output terminals of the function generators; a second set of multiplexers (1010 ₀-1010 ₃, 1016 ₀-1016 ₃) configured to route data values to the write data input terminals of the function generators; and a set of interconnect lines, wherein each of the lines is connected to a control terminal of one of the multiplexers in the first set of multiplexers, and to an input terminal of one of the multiplexers in the second set of multiplexers.
 15. The CLB of claim 14, wherein each of the function generators further comprises a write enable terminal, wherein each of the write enable terminals is coupled to a subset of the interconnect lines by write control logic.
 16. A configurable logic block (CLB) comprising: a plurality of function generators, each having a write enable terminal and a read data output terminal; a first set of hierarchically connected multiplexers (F50-F53, FX0-FX3) configured to route data values from the read data output terminals of the function generators; a plurality of write control circuits configured to provide write enable signals to the write enable terminals of the function generators; and a set of interconnect lines wherein each of the lines is connected to a control terminal of one of the multiplexers in the first set of multiplexers, and wherein a subset of the interconnect lines is coupled to each of the write control circuits. 